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-- Company: 
-- Engineer:
--
-- Create Date:   11:59:40 05/17/2011
-- Design Name:   
-- Module Name:   C:/Users/Geoff/Documents/Degree/CSSE2000/Vcode/theproject/ControlUnit_test.vhd
-- Project Name:  theproject
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: proc_controlunit
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY ControlUnit_test IS
END ControlUnit_test;
 
ARCHITECTURE behavior OF ControlUnit_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT proc_controlunit
    PORT(
         clk : IN  std_logic;
         rst : IN  std_logic;
         en : IN  std_logic;
         instruction : IN  std_logic_vector(15 downto 0);
         immediate_value : OUT  std_logic_vector(7 downto 0);
         register_en : OUT  std_logic;
         register_p_0_write : OUT  std_logic;
         register_p_0_write_source : OUT  std_logic;
         register_p_0_addr_direct : OUT  std_logic_vector(3 downto 0);
         register_p_1_addr_direct : OUT  std_logic_vector(3 downto 0);
         alu_en : OUT  std_logic;
         alu_b_source : OUT  std_logic;
         alu_mode : OUT  std_logic;
         pc_en : OUT  std_logic;
         pc_jump_source : OUT  std_logic;
         pc_mode : OUT  std_logic;
         sreg_en : OUT  std_logic;
         sreg_source : OUT  std_logic;
         sreg_bit_en : OUT  std_logic;
         sreg_bit_index : OUT  std_logic_vector(2 downto 0);
         sreg_bit_value_in : OUT  std_logic;
         sreg_jump_en : OUT  std_logic;
         mem_en : OUT  std_logic;
         mem_addr_source : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
   signal en : std_logic := '0';
   signal instruction : std_logic_vector(15 downto 0) := (others => '0');

 	--Outputs
   signal immediate_value : std_logic_vector(7 downto 0);
   signal register_en : std_logic;
   signal register_p_0_write : std_logic;
   signal register_p_0_write_source : std_logic;
   signal register_p_0_addr_direct : std_logic_vector(3 downto 0);
   signal register_p_1_addr_direct : std_logic_vector(3 downto 0);
   signal alu_en : std_logic;
   signal alu_b_source : std_logic;
   signal alu_mode : std_logic;
   signal pc_en : std_logic;
   signal pc_jump_source : std_logic;
   signal pc_mode : std_logic;
   signal sreg_en : std_logic;
   signal sreg_source : std_logic;
   signal sreg_bit_en : std_logic;
   signal sreg_bit_index : std_logic_vector(2 downto 0);
   signal sreg_bit_value_in : std_logic;
   signal sreg_jump_en : std_logic;
   signal mem_en : std_logic;
   signal mem_addr_source : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: proc_controlunit PORT MAP (
          clk => clk,
          rst => rst,
          en => en,
          instruction => instruction,
          immediate_value => immediate_value,
          register_en => register_en,
          register_p_0_write => register_p_0_write,
          register_p_0_write_source => register_p_0_write_source,
          register_p_0_addr_direct => register_p_0_addr_direct,
          register_p_1_addr_direct => register_p_1_addr_direct,
          alu_en => alu_en,
          alu_b_source => alu_b_source,
          alu_mode => alu_mode,
          pc_en => pc_en,
          pc_jump_source => pc_jump_source,
          pc_mode => pc_mode,
          sreg_en => sreg_en,
          sreg_source => sreg_source,
          sreg_bit_en => sreg_bit_en,
          sreg_bit_index => sreg_bit_index,
          sreg_bit_value_in => sreg_bit_value_in,
          sreg_jump_en => sreg_jump_en,
          mem_en => mem_en,
          mem_addr_source => mem_addr_source
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ms.
      wait for 100 ms;	

      wait for clk_period*10;

      en <='1';
	      wait for clk_period*10;	
		en <='0';

      wait;
   end process;

END;
